This invention relates to an input interface circuit for a logic device (e.g., an integrated injection logic device), and more particularly to an input interface circuit characterized by hysteresis.
Japanese Patent Disclosure (KOKAI) No. 54-102955 sets forth an input interface circuit for an integrated injection logic (I.sup.2 L) device. This interface circuit has a single threshold voltage which is designed to have a given level. However, the interface circuit is too sensitive to the ripples of an input signal caused by, for example, external noises.
Another Japanese Patent Disclosure (KOKAI) No. 51-130160 also discloses an input interface circuit. This interface circuit has first and second threshold voltages, and consequently an input signal to said interface circuit and an output signal therefrom are jointly characterized by hysteresis. The hysteresis characteristic suppresses the malfunction of the input interface circuit caused by external noises. However, the threshold voltage level of the interface circuit is governed by the characteristic of the transistor used, that is, the base-emitter voltage VBE and saturated collector voltage VCE (SAT) of the transistors. In other words, the threshold voltage level of said interface circuit is fixed at only two values "2VBE" and "VBE+VCE(SAT)". However, the available hysteresis is narrow (i.e., about 0.5 V). The disclosed interface circuit has a further drawback in that a low impedance is applied.